Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile and other applications. The technology used to manufacture image sensors, and in particular complementary metal-oxide-semiconductor (“CMOS”) image sensor, has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.
FIG. 1A is a circuit diagram illustrating pixel circuitry of a four-transistor (“4T”) pixel cell 100 within an image sensor array. Pixel cell 100 may be repeated and organized into rows and columns of the image sensor array. Pixel cell 100 includes a photodiode 101, a transfer transistor 102, a reset transistor 103, a source-follower (“SF”) transistor 104, a row select (“RS”) transistor 105, and a floating diffusion (“FD”) node 106.
During operation, transfer transistor 102 receives a transfer signal TX, which causes transfer transistor 102 to transfer the charge accumulated in photodiode 101 to FD node 106. Reset transistor 103 is coupled between a power rail VDD and FD node 106 to reset the pixel cell (e.g., discharge or charge FD node 106 and photodiode 101 to a preset voltage) under the control of reset signal RST. Floating diffusion node 106 is coupled to the gate terminal of SF transistor 104. SF transistor 104 has its channel coupled between power rail VDD and RS transistor 105. SF transistor 104 operates as a source-follower, providing a high impedance connection to FD node 106. RS transistor 105 selectively couples the output of pixel cell 100 to bit line 107 (also referred to as a column readout line) under the control of signal RS.
FIG. 1B is a timing diagram 110 for pixel cell 100 in FIG. 1A during normal operation. In normal operation, photodiode 101 and FD node 106 are reset during a reset phase by temporarily asserting reset signal RST and transfer signal TX. As seen in FIG. 1B, after the reset phase, an integration phase is commenced by de-asserting transfer signal TX and reset signal RST, and permitting incident light to charge photodiode 101. The voltage or charge on photodiode 101 is indicative of the intensity of light incident of photodiode 101 during the integration period. The readout phase is commenced before the end of the integration phase, by asserting reset signal RST to reset FD node 106 to the reset voltage VRST. VRST approximately equals the power rail VDD minus the threshold voltage VTH of reset transistor 103. After floating diffusion node 106 has been reset, row select signal RS and a sample signal SHR (sample-hold-reset) are asserted, which couples FD node 106 to a sample and hold circuit (not shown) via RS transistor 105 and bit line 107. After reset voltage VRST is sampled, sample signal SHR is de-asserted. The end of the integration phase occurs after the de-assertion of sample signal SHR. Transfer signal TX is then asserted to couple photodiode 101 to floating diffusion node 106 and the gate terminal of SF transistor 104. As the photo-generated charge carriers (e.g., electrons) accumulated on photodiode 101 are transferred to FD node 106, the voltage at FD node 106 decreases since electrons are negative charge carriers. After charge transfer is complete, transfer signal TX is de-asserted. After transfer signal TX is de-asserted, sample signal SHS (sample-hold-signal) is asserted and the voltage at FD node 106, VSIG, is sampled.
When reset signal RST is asserted, during the reset phase and the beginning of the readout phase, the channel region of reset transistor 103 is inverted and electrons are injected into the channel. When reset signal RST is de-asserted, some charges in the channel will be injected to the terminal coupled to power rail VDD and other charges will be injected to the terminal coupled to FD node 106. The injection of charge into FD node 106 lowers the potential of FD node 106.
FIG. 1C is a graph illustrating the voltage at FD node 106 during the time periods illustrated in FIG. 1B. During the reset phase (and the beginning of the readout phase when reset voltage is sampled by a sample and hold circuit (not shown)), reset signal RST is asserted and FD node 106 is reset to reset voltage VRST. As seen in FIG. 1C, when reset signal RST is de-asserted, the voltage at FD node 106 falls to a charge injection voltage VCI. The difference between reset voltage VRST and charge injection voltage VCI is ΔV. An increase in the voltage level of reset signal RST may result in an increase of ΔV. The decrease in the potential of FD node 106 decreases the floating diffusion voltage swing and consequently decreases the conversion gain of pixel cell 100. Charge injection in the reset transistor can be reduced by increasing the channel length of the reset transistor; however, this either increases the size of pixel cell 100 or decreases the fill factor of pixel cell 100. The detrimental effects of charge injection can also be reduced by reducing clock speeds; however, this leads to a slower speed image sensor.
The conversion gain of pixel cell 100 is defined as the ratio of the change in voltage at FD node 106 during charge transfer to the change in charge transferred to FD node 106. Conversion gain is inversely proportional to the capacitance of FD node 106. A high conversion gain can be beneficial in improving low-light sensitivity. For traditional image sensors, conversion gain can be increased by reducing the capacitance of FD node 106; however, as pixel cells continue to shrink, pixel saturation or overexposure in bright environments is becoming more acute.